HighlightsΒΆ

  • Use the GUI to quickly draw timing diagrams.

  • Use simple Python scripts to draw timing diagrams, generate test vectors, build testbenches, or add new features to the program.

  • Quickly find timing violations in digital logic.

  • Use synchronous and combinatorial logic functions to simplify drawing more complex diagrams.

  • Draw diagrams directly from VHDL Simulations App Note

  • Draw diagrams directly from Verilog Simulations App Note

  • Read VCD files and convert to timing diagrams automatically

  • Diagrams are saved in simple text format which can modified with text editor.

  • Save diagrams in many image file formats and scalable vector formats so they can easily be added to technical documentation.

  • Use with Visio. Save diagram as SVG and open with Visio. Ungroup to edit any part of the diagram.

  • Written in Java, it runs on any platform that supports the Java Run-time Environment, JRE1.6.0 or Java Development Kit JDK1.6.0 or newer