Script Examples

Drawing a Timing Diagram

The script draw_diagram.py is shown below

 1# start a new timing diagram
 2if taApp.getFileName() != "new.tim":
 3    taApp.fileNew("TimingDiagram")
 4
 5# get the reference to the timing diagram
 6td = taApp.getTimingDiagram()
 7
 8# add the signals
 9dclock  = td.addDigitalClock("test-clk", 20.0e6, "H")
10dsignal = td.addDigitalSignal("mem_read", "L")
11dbus    = td.addDigitalBus("mem_add[15:0]", "CC00", "Hex")
12
13# add pulses to the signal and bus
14td.addPulse(dsignal, 50.0e-9, 100e-9, "H")
15td.addPulse(dbus, 30.0e-9, 120e-9, "CC05")
16
17# add 2 edges to the signal
18td.addEdge(dsignal, 200.0e-9, "H")
19td.addEdge(dsignal, 250.0e-9, "L")
20
21# add 2 edges to the bus
22td.addEdge(dbus, 180.0e-9, "CCCC")
23td.addEdge(dbus, 270.0e-9, "CD00")

Creating a D Flip Flop

The script dff.py is shown below

 1# start a new diagram
 2if taApp.getFileName() != "new.tim":
 3    taApp.fileNew("TimingDiagram")
 4
 5# get the current timing diagram
 6td = taApp.getTimingDiagram()
 7
 8# add the CLK, D, and Q signals
 9clk  = td.addDigitalClock("CLK",20.0e6,"H")
10sigD = td.addDigitalSignal("D","L")
11sigQ = td.addDigitalSignal("Q","L")
12
13# add a pulse and two edges to the D input
14sigD.addPulse(75.0e-9,125.0e-9,"H")
15sigD.addEdge(175.0e-9,"H")
16sigD.addEdge(225.0e-9,"L")
17
18# define and add a UserDelay
19clk2q_min = 2.0e-9
20clk2q_typ = 4.0e-9
21clk2q_max = 6.0e-9
22clk2q_dly = td.addUserDelay("CLK2Q",clk2q_min,clk2q_typ,clk2q_max,"DFF Clock to Q ouput delay");
23
24# get the clock edge list
25# loop on each edge in the list
26#    if its the rising edge
27#        save the edge time
28#        save the D input state
29#        if next state doesn't equal last state and
30#           this new edge time is greater the last edge time
31#           add the new edge
32#           add a delay to the edge
33clk_edge_list = clk.getEdgeList()
34ls = "L"
35for clk_edge in clk_edge_list:
36    if clk_edge.getNextState() == "H":
37        et = clk_edge.getPt2()
38        ns = sigD.getStateAtTime(et)
39        if ((ns != ls) and (et + clk2q_min > sigQ.getLastEdgePt2())):
40            sigQ_edge = sigQ.addEdge(et,ns)
41            td.addDelay(clk2q_dly,clk_edge,sigQ_edge)
42        ls = ns

Dumping Signal Values

The script dump_edges.py is shown below

 1import ta_utils
 2from org.dmad.ta import DigitalClock
 3
 4outfile = ta_utils.setOutputFileName("dump_edges.txt")
 5td = taApp.getTimingDiagram()
 6
 7signal_list = td.getSignalList()
 8
 9clock_signal = None
10for signal in signal_list:
11    if isinstance(signal, DigitalClock):
12        clock_signal = signal
13    else:
14        outfile.write("%s " % (signal.getName()))
15
16outfile.write("\n")
17
18for clock_edge in clock_signal.getEdgeList():
19    if clock_edge.getNextState() == "H":
20        edge_time = clock_edge.getPt2()
21        for sig in signal_list:
22            if sig != clock_signal:
23                outfile.write("%s " % (sig.getStateAtTime(edge_time)))
24        outfile.write("\n")
25
26outfile.close()

Generating VHDL Test Vectors

The script vhdl_test_vectors.py is shown below

 1import ta_utils
 2
 3from org.dmad.ta import DigitalSignal
 4from org.dmad.ta import DigitalBus
 5from org.dmad.ta import DigitalClock
 6
 7out_file = ta_utils.setOutputFileName("vhdl_test_vectors.txt")
 8td = taApp.getTimingDiagram()
 9ts = td.getTimeScale()
10ts_text = ta_utils.getTimeScaleText(ts)
11
12signals = td.getSignalList()
13for sig in signals:
14    i = 0
15
16    out_file.write("%s <= " % (sig.getName()))
17
18    for edge in sig.getEdgeList():
19        if isinstance(sig, DigitalSignal) or isinstance(sig, DigitalClock):
20            line = "'%s'"  % (edge.getNextState())
21            if i != 0:
22                line = "    %s after %s %s" % \
23                    (line,
24                     ta_utils.round3Places(edge.getPt2() / ts),
25                     ts_text)
26        elif isinstance(sig, DigitalBus):
27            state_format = {
28                "Hex":  "X\"",
29                "Bin":  "\""
30            }
31
32            sStart = state_format[sig.getStateFormat()]
33
34            line = "%s%s\"" % (sStart, edge.getNextState())
35            if i != 0:
36                line = "    %s after %s %s" % \
37                    (line,
38                     ta_utils.round3Places(edge.getPt2() / ts),
39                     ts_text)
40
41        if ( i == len(sig.getEdgeList())-1):
42            out_file.write("%s;\n\n" % (line))
43        else:
44            out_file.write("%s,\n" % (line))
45
46        i += 1
47out_file.close()