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Using the TimingAnalyzer, you can quickly and easily draw timing diagrams, build
libraries of timing diagrams, and perform timing analysis on logic designs. 
Setup and hold violations are reported to indicate logic design problems.

Timing diagrams can be created with the GUI, Python scripts, VCD files, and logic
simulations. The TimingAnalyzer has been designed with focus on timing analysis 
but is much more than just a simple drawing program. Check out the complete list 
of features listed on the features page.


Comments and feedback are always welcome.

Dan Fabrizio

timinganalyzer@gmail.com



.. toctree::
   :maxdepth: 1
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   features
   screenshots_and_videos
   getting_started
   quick_guide
   step_by_step_examples
   user_manual
   scripting_manual
   app_notes
   timing_diagram_library
   download
   faq
   google_group
   contact
   license