App Notes

• Generating Timing Diagrams from Verilog Simulations
  • Introduction
  • The Verilog Example
  • Output Start and Finish Timing Diagram Functions
  • Add and Monitor Each Signal Functions
  • The SRAM Timing Diagram Component
• Generating Timing Diagrams from VHDL Simulations
  • The VHDL Example
  • Initialize the Timing Diagram Functions
  • Add and Monitor Each Signal Functions
  • Finalize Timing Diagram Functions
  • The SRAM Timing Diagram Component
• Introduction to Timing Analysis
  • Combinatorial Logic
  • Synchronous Logic
  • Register to Register Path
  • Register to Register Path with Clock Skew
  • Register to Register Path with Clock Jitter